Understand your graphics memory requirements for wearable devices
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Even with the most conservative estimates, market demand for Internet of Things (IoT) and wearable devices will triple by 2020. This means that there will be 50 billion pieces of equipment worldwide. This will create a need for a new generation of display drivers and frame buffers, a type of memory that is different from the memory used in traditional displays. Although embedded RAM can meet the needs of the first generation of wearable devices, today's HD and large wearable displays require much larger frame buffer memory. These requirements differ from traditional PC and TV displays because they use battery power and energy efficiency is a major design constraint. Most of the latest wearable devices will have extremely high space efficiency and energy efficiency, so that they will be able to work for several days or even weeks after they are fully charged, while still performing a variety of complex operations. This is why we need a new generation of display drivers.
To understand frame buffer requirements for wearable devices, let's first examine the architecture of the graphics system. Each graphics system consists of three components: hardware, a graphics library, and an application that uses it.
Graphics libraries and applications are controlled by software, while hardware is controlled by a frame buffer, which is a continuous high-throughput memory. Each memory cell in the frame buffer corresponds to one pixel on the screen. The pixel intensity is determined by its voltage.
The resolution of the display is determined by the following factors:
Number of scanning lines The number of pixels per line The number of bits per pixel takes a 1024x76824-bit image as an example. It is the most common screen resolution for PCs.
1024X768X24=18.9Mb
This is the minimum capacity required for the frame buffer to support this display. However, if it is a dynamic display with video capabilities, only one such memory is not enough. This puts a throughput requirement on the frame buffer.
For a video at 30 frames per second (fps) at the above resolution, the maximum throughput is: 18.9x30 = 566 Mbps.
As described above, each memory cell in the frame buffer corresponds to one pixel on the screen. For an n-bit color display, each of the n bits is a single bit plane (eg, 24-bit color has 24 bit planes). N memory cells will store the state of each pixel and binary values ​​from each n-bit plane are loaded into corresponding locations in memory. The final binary number is interpreted as an intensity value between 0 and 2n–1. It is then converted by a digital-to-analog converter to an analog voltage between 0 and the maximum voltage to achieve 2n intensities.
Two factors determine the type of frame buffer used by the display: capacity and throughput. Increasing the resolution of the image requires more memory, while increasing the fps of the video requires higher throughput. There are two ways to meet this requirement: increase the frame buffer's capacity and throughput, or reduce throughput by increasing the frame buffer's capacity (eg, double the former and halve the latter). By increasing the capacity of the frame buffer (usually integrating multiple frame buffers in a single chip), we can reduce throughput because the input-output cycles that the chip must experience are reduced. For example, after doubling the capacity, two frames can be stored in a buffer at the same time, which means that the number of times the buffer is called/referenced in a given time is reduced by half, thus achieving a lower throughput . Therefore, memory is divided into two categories: high density and high throughput. This aspect will be discussed later in this article.
After carefully observing the specifications of the latest generation of computer graphics processors (GPUs) from Nvidia and AMD, we found that the memory capacity has increased significantly, usually to several GB. This is because most modern GPUs are designed for games and high-definition rendering applications, and there are many additional functions that take up memory space: MSAA (uses sampling frequency to double buffer capacity), prefetching, shadow buffers, Delay rendering and effects. Even the functions we take for granted, such as window scrolling, require extra buffer space. Most game buffers use triple buffering (three buffers per frame) and HDR (normal HDR depth is 64 bits instead of 24 bits). Many of these high-end GPUs also support multiple HD displays, which means that a dedicated buffer is built into each display.
However, most wearable devices and portable devices do not need these functions because of their small display. The ideal approach is to use the MCU's embedded memory resources as a frame buffer. It will have the highest throughput and it is the easiest to implement. However, for a new generation of displays in wearable devices, the memory of most MCUs is not enough. In addition, increasing program complexity requires the use of larger embedded memory as the MCU's level 1 cache. For most contemporary wearable devices, the resolution of the display is QVGA (QuarterVideo Graphics Array), and for these displays, the following specifications will suffice: 24-bit | 480*360 | 30fps. For wearable devices, they mean that the number of pixels per inch (ppi) reaches 300. The memory requirement of this kind of display is 4Mb memory whose throughput is 120Mbps. However, future devices will be equipped with a much higher resolution display, over 400ppi, which is comparable to many of the latest generation of mobile phones. For a display of the same size, the increasing ppi means that the frame buffer capacity also increases accordingly. As mentioned above, there are two ways to implement a frame buffer of this capacity: a 4 Mb buffer with a throughput of about 120 Mbps or a 16 Mb buffer with a throughput of about 30 Mbps. In both of these approaches, small-capacity buffers offer numerous benefits - smaller size (chip or CSP), lower power consumption, lower cost, and more choices (as capacity density increases, manufacturers and product categories There will be less and less.) For wearable devices, size, power consumption, and cost are the most important determinants of all device components.
The most widely used frame buffer memory is dynamic RAM (DRAM), although the most common highest-performance memory is static RAM (SRAM). DRAM consumes more power than SRAM and has lower throughput than the latter. Although the performance of SRAM is extremely high and it is an ideal choice for the latest generation of portable devices, most battery-backed devices do not use them because SRAM's product range is small, with low-density products and a maximum of 128 Mbits. The structure of the SRAM memory cell is relatively complex and consists of six transistors, and the DRAM memory cell is composed of one transistor and one capacitor. This is why SRAM is limited in its increased density, and this has proven to be its biggest limitation. Although SRAM is not used in traditional consumer electronics devices (PCs, TVs, mobile phones, etc.) due to this limitation, SRAM is not a bad thing for wearable devices, considering that the frame buffer memory capacity required by wearable devices is small. In addition, in these devices, higher performance (higher throughput is equivalent to lower power consumption) is also a big advantage of SRAM.
With the return of the need for high performance, especially low power consumption, the type of memory that was once considered extinct - SRAM - seems to rejuvenate. You can read this article to learn about SRAM in next-generation wearables and IoT devices. The article describes the use of SRAM beyond frame buffers: from memory expansion to data logging.
Many leading SRAM vendors have introduced a series of innovative technologies, mainly to meet the needs of wearable systems: from higher reliability to new packaging forms. In the field of high-definition video recording and processing, Cypress also has a different series of HD frame buffers. For more information on the frame buffer memory configuration and the HD frame buffer family, see the following application note: Using High Density Programmable FIFOs in Video and Imaging Applications.